1. Field of the Invention
The present invention relates to a chip-enable-signal generation circuit usable for both a device having m chips at maximum and a device having 2m chips at maximum or usable for both a device having m chips at maximum and a device having 2m+n chips at maximum, and, also, relates to a memory device designed to have such a chip-enable-signal generation circuit implemented thereon. The present invention particularly relates to a chip-enable-signal generation circuit which can generate an appropriate chip-enable-signal even if chip information is not supplied externally, and relates to a memory device designed to have such a chip-enable-signal generation circuit implemented thereon.
Flash memories have been making a progress in the market. Flash memories are EEPROMs having a function to erase the memory contents at once. Since flash memories can be made small with high circuit density, their applications to various electronics equipment are anticipated.
Because of the wide range of applications, memory cards having flash memories therein are expected to be provided in a variety of product types, ranging from one having several flash memories to one having several dozens of flash memories in accordance with the types of electronics equipment to which they are applied. It is difficult, however, to provide different types of controllers for different types of memory cards according to the number of flash memories. It is necessary to cope with this situation without increasing the number of terminals, for example.
2. Description of the Related Art
Methods of generating a chip-enable signal supplied to flash memory chips or the like include generating a chip-enable signal by allocating the chip-enable signal directly to each bit of a binary code, or generating a chip-enable signal by decoding a binary code.
When generating a chip-enable signal for m chips, for example, the former method allocates a chip-enable signal to each bit of a m-bit binary code so as to indicate an enable status of a selected one of the m chips.
When a first one of four chips is to be enabled, for example, a chip-enable signal [0001] is generated. When the second chip is to be enabled, a chip-enable signal [0010] is generated. By the same token, a chip-enable signal [0100] is generated in order to enable the third chip. Finally, a chip-enable signal [1000] enables the fourth chip.
When generating a chip-enable signal for 2m chips, the latter method decodes a m-bit binary codes, and generates a chip-enable signal indicative of an enable status of a selected chip.
In order to enable a first one of 16 chips, for example, a binary code [0001] is decoded to generate a chip-enable signal [0000000000000001]. When the second chip is to be enabled, a binary code [0010] is decoded to generate a chip-enable signal [0000000000000010]. Further, a binary code [0011] is decoded to generate a chip-enable signal [0000000000000100], which is to enable the third chip.
The former method generates a chip-enable signal for m chips by using a m-bit code, so that this method is typically used when the number of chips is relatively small. The latter method generates a chip-enable signal for 2m chips by using a m-bit code, so that this method is typically used when the number of chip is relatively large.
When there is a need to supply a chip-enable signal to flash memory chips or the like, a controller for generating the chip-enable signal usually generates the chip-enable signal based on the former method in the case of a small number of chips, and generates the chip-enable signal based on the latter method in the case of a large number of chips.
In order to make a single controller usable for both a device having a small number of chips and a device having a large number of chips, the controller needs to be informed whether it is implemented on the device having a small number of chips or on the device having a large number of chips. In this manner, the controller can select an appropriate method of generating a signal.
In order to achieve this, a related-art controller is provided with a dedicated terminal for signal exchange. This dedicated terminal is used for informing the controller of the number of chips or an appropriate method of generating a chip-enable signal.
In such a configuration, the controller already having many terminals for signal exchanges with external sources needs to have an extra terminal dedicated for this purpose.
An increase in the number of terminals hinders an effort to miniaturize a controller size. Use of the configuration described above results in the miniaturization of a controller device being undermined.
Devices having flash memories implemented thereon are typically expected to be provided in a small size by utilizing a relatively small size of the flash memories. The configuration of the related art, therefore, goes against this expectation for miniaturization.
Accordingly, there is a need for a chip-enable-signal generation circuit which is usable for both a device having m chips at maximum and a device having 2m chips at maximum or usable for both a device having m chips at maximum and a device having 2m+n chips at maximum, and can generate an appropriate chip-enable signal without requiring external help to obtain information about chips on the device, and, also, there is a need for a memory device suitable for having such a chip-enable-signal generation circuit implemented thereon.
Accordingly, it is a general object of the present invention to provide a chip-enable-signal generation circuit and a memory device which can satisfy the respective need described above.
It is another and more specific object of the present invention to provide a chip-enable-signal generation circuit which is usable for both a device having m chips at maximum and a device having 2m chips at maximum or usable for both a device having m chips at maximum and a device having 2m+n chips at maximum, and can generate an appropriate chip-enable signal without requiring external help to obtain information about chips on the device.
It is yet another object of the present invention to provide a memory device suitable for having such a chip-enable-signal generation circuit as described above implemented thereon.
In order to achieve the above objects according to the present invention, a circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.
According to the circuit as described above, the chip-enable signal and the chip-enable generation signal include the same bit pattern when the chip number is the specific number. Because of this feature, a predetermined one of the chips specified by the specific number can be enabled and accessed by using the specific number regardless of whether the first device with m chips is provided or the second device with more than m chips is provided, no matter which one of the chip-enable signal or the chip-enable generation signal is initially selected. The circuit thus can obtain information about whether the first device is in use or the second device is in use by accessing the predetermined one of the chips specified by the specific number if the information is stored in the predetermined one of the chips.
The circuit as described above further includes an acquisition unit which obtains information about whether the circuit is used for the first device or is used for the second device, the information being obtained by accessing one of the chips that is enabled by the chip-enable signal corresponding to the specific number, and a setting unit which sets a selection signal based on the information obtained by the acquisition unit, the selection signal controlling the selection unit with regard to whether the chip-enable signal generated by the first generation unit is selected or the chip-enable generation signal generated by the second generation unit is selected.
By use of the circuit described above, a chip specified by the specific chip number is enabled when the specific chip number is issued, no matter whether the first device is in use or the second device is in use. When the information about whether the first device is in use or the second device is in use is stored in the chip specified by the specific chip number, the acquisition unit can ascertain which one of the first device and the second device is in use by issuing the specific chip number. In this manner, the circuit can subsequently generate an appropriate chip-enable signal without requiring external help to obtain information about a configuration of the chips implemented on the employed device.
Further, a memory device according to the present invention includes a CPU, one or more memories capable of retaining data thereof even when power is not supplied thereto, and a controller which controls the one or more memories in accordance with instructions from the CPU, wherein the one or more memories store information necessary for operation thereof, and the CPU controls the controller to read the information from the one or more memories when the memory device starts an operation thereof and to store the information in a register so that a program executed by the CPU can refer to the information stored in the register.
According to the memory device described above, memories that can retain data thereof during a time when power is not supplied stores information necessary for operation of the memory device, and the information is loaded to a register that is referred to by a program when the memory device starts an operation thereof. Because of this configuration, there is no need to provide an extra connector terminal to the memory device for the purpose of informing the memory device of the information necessary for the operation thereof. Further, the operation information of the memory device can be easily modified by rewriting the operation information stored in the memories.
Further, a memory device according to the present invention includes a CPU, memory chips, and a generation unit which supply either a chip-enable signal that enables one of the memory chips or a chip-enable generation signal that is to be decoded to enable one of the memory chips, wherein the CPU controls the generation unit to supply the chip-enable signal to attempt to access one of the memory chips enabled by the chip-enable signal when the memory device starts an operation thereof, and subsequently controls the generation unit to supply the chip-enable signal when the attempt is successful and to supply the chip-enable generation signal when the attempt is unsuccessful.
Moreover, a memory device according to the present invention includes a CPU, memory chips, and a generation unit which supply either a chip-enable signal that enables one of the memory chips or a chip-enable generation signal that is to be decoded to enable one of the memory chips, wherein the CPU controls the generation unit to supply the chip-enable generation signal to attempt to access one of the memory chips enabled by the chip-enable generation signal when the memory device starts an operation thereof, and subsequently controls the generation unit to supply the chip-enable generation signal when the attempt is successful and to supply the chip-enable signal when the attempt is unsuccessful.
In the memory device described above, both the chip-enable signal supplied to the memories and the chip-enable generation signal that is to be decoded to generate a chip-enable signal supplied to the memories are generated, and the chip-enable signal is selected and supplied to the memories when no decoder is provided, whereas the chip-enable generation signal is selected and supplied to a decoder when such a decoder is provided. In this manner, a decision is easily made as to whether to supply the chip-enable signal or to supply the chip-enable generation signal.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.